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Performance Modeling of VIA-Switch FPGA for Device-Circuit-Architecture Co-Optimization

机译:用于设备电路架构共同优化的VIA-Swits FPGA性能建模

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This paper discusses performance modeling for FPGA (Field Programmable Gate Array) which uses an emerging switching device called a via-switch for programmable interconnects and logic configurations. With the derived model, we can evaluate how the overall chip-level performance is affected by various design parameters such as device characteristics, threshold voltages, layout structures, FPGA architectures, and so on, which enables device-circuit-architecture co-optimization under a target fabrication process. Performance optimization examples are shown assuming a 65 nm CMOS process such as the threshold voltage turnings for the minimum energy and the minimum ED-product operations, and cross-point decimation for energy reduction.
机译:本文讨论了FPGA(现场可编程门阵列)的性能建模,其使用称为可编程互连和逻辑配置的通孔开关的新出现开关设备。通过派生模型,我们可以评估整体芯片级性能如何受到各种设计参数的影响,如设备特性,阈值电压,布局结构,FPGA架构等,这使得设备电路架构协调目标制造过程。假设65nm CMOS工艺示出了性能优化示例,例如用于最小能量的阈值电压转弯和最小ED-MATERM操作,以及用于能量减少的交叉点抽取。

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