LDPC decoder implementation using FPGA

摘要

This paper presents a partial-parallel LDPC decoder based on sum-product algorithm with high throughput. The hardware implementation of decoder considers design issues with respect to FPGA and time scheduling is proposed based on modified TPMP1 algorithm in order to reduce the number of clock cycles, hardware resources and power. The decoder is implemented for a code length of 672 whit rate of 3/4, maximum throughput of 3360 Mbps in maximum frequency of 280 MHz and provides power of 150 mW.