3D integration relying on novel vertical interconnectiontechnologies opens the gate to powerful microelectronicsystems in ultra-thin packages answering the demand of themobile market.Among these, die-to-wafer stacking is a key enablingtechnology for 2.5D as well as for 3D with technologicalchallenges driven by, in one hand, the increase of the diesurface and the number of I/Os and, on the other hand, thereduction of the vertical dimensions. In our integration schemewe have achieved flip chip stacking (or Face to Face) of 35μm ultra-thin dies with low stand-off (< 15 μm) copper microbumpsand tin-silver-copper solders (SAC).Ultra-thin dies are prepared using dicing before grinding(DBG) technique. After DBG, plasma stress release process isapplied to the backside of the singulated chips.Copper μbump technology is challenging with this verylow profile stacking since the current flip chip process is nolonger adapted to this geometry and that the die flatnesstolerance become very critical to obtain a high soldering yield.Process improvements have been achieved on the copperpillar fabrication itself with several metallurgy stackconfigurations as well as new processes using damascenetechniques.Furthermore, innovative technologies have been deployedon the pick and place and collective soldering processes.Intermetallic formation during reflow process is achievedthrough transient liquid phase (TLP) reaction leading tothorough consumption of the tin layer and to the formation ofCu_6Sn_5 and Cu_3Sn compounds.Capillary underfill is finally successfully applied in thenarrow die-to-wafer gap by jetting technique.After optimization, electrical tests show a very high yieldclose to 100% over a representative number of fully populatedwafers.Reliability tests have also been carried out at wafer levelexhibiting no significant resistance increase or yield loss over1000 thermal cycles between -40 and +125°C.
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