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One Micron Damascene Redistribution for Fan-Out Wafer Level Packaging using a Photosensitive Dielectric Material

机译:一种微米镶嵌可用于使用光敏介电材料的扇出晶片级包装的再分布

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This study investigates creation of 1.0μm RDL structures by a damascene process utilizing a photosensitive permanent dielectric material. The advantage of the photosensitive dielectric approach is that the Cu overburden removal does not affect the quality of the embedded Cu lines. In comparison, for a semi-additive process the Cu seed etch affects the final dimensions of the RDL lines [1]. Damascene processing of RDL will also result in a flat wafer surface which greatly improves the lithographic performance for subsequent layers. Finally, the Cu line is surrounded on the sides and bottom by a Ti barrier layer which provides a Cu diffusion barrier for enhanced reliability [2,3]. The completed 1.0μm RDL damascene process is evaluated using a test chip design that includes metrology structures for in-line monitoring and CDSEM measurements, and comb and serpentine electrical test structures. The electrical results for the damascene process show significant advantages compared to the semi-additive process.
机译:本研究通过利用光敏永久电介质材料调查通过镶嵌工艺创建1.0μm的RDL结构。光敏电介质方法的优点是Cu覆盖层去除不会影响嵌入式Cu线的质量。相比之下,对于半添加过程,Cu种子蚀刻影响RDL线的最终尺寸[1]。 RDL的镶嵌处理也将导致扁平晶片表面,这极大地提高了后续层的光刻性能。最后,Cu线通过Ti阻挡层围绕侧面和底部,其提供Cu扩散屏障,以增强可靠性[2,3]。使用测试芯片设计评估完成的1.0μm的RDL镶嵌过程,包括用于在线监测和CDSEM测量的计量结构,以及梳状和蛇形电测试结构。与半添加过程相比,镶嵌过程的电气结果显着显示出显着的优势。

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