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Thermo-mechanical Stress of underfilled 3D IC packaging

机译:底层3D IC包装的热机械应力

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摘要

In recent years, there has been a dramatic proliferation of research concerned with electronic products because of more various functions are integrate into the device and product's size has become smaller. As a result of these functional requirements, through silicon via (TSV) was investigated, this are getting considerable attentions not only from reducing the packaging size but also from shortening the interconnection's distance that can achieve the effect of enhancing signal transmission. TSVs are the vertical hole through the stacked IC, and they are also responsible for transferring signals between the ICs. Thus, they can improve the time delay of the signal transduction and allow better electrical performance than stacked ICs with wire bonding technology. However, a review of the literature indicates that electronic components will be affected easily by environmental factors such as humidity, pressure, and temperature. In general, the stacked ICs with TSV structure is easily affected by temperature changes than others factors since each material have different thermal expansion. In very recently, the stacked IC packaging has been primarily concerned with thermo-mechanical loadings than traditional single IC packaging, which leads some problems such as via cracking, die cracking and interfacial delamination and so on. The above problems not only affect the performance of the device but also lead the device fail. Hence, most of the studies [1–9] are focus on discussing thermal mechanical loading with simulation method. Some of them discuss the relationship between the TSV shape and the stresses [4, 5]. In addition, most of people just build local TSV structure to do their research [4–9]. Although it can save more time but it also increase the error percentage with real situation. And this paper build the three dimensional four layers stacked IC packaging model from Hsieh [1]'s paper which can more close to real situation. And setting the str- cture to be simulated from the temperature 150°C to −50°C which is as retreat temperature. This paper use ANSYS software which is based on finite element theory in order to reduce time used and save cost, as finite element simulation can provide results more quickly and cheaply than experiments. Moreover, the research mainly analyzes the maximum von-Mises stress in TSVs and micro-bumps. Besides, this paper will sort out geometries and material properties of underfill which will serious affect von-Mises stress value by Design of Experiments (DoE) analysis. Through the DoE analysis, the critical factors are selected as main design factors to reduce the von-Mises stresses. This study can provide the significant information to effectively design the products and increase the reliability. This information can also eliminate the testing time.
机译:近年来,出现了涉及电子产品,因为更多的各种功能研究的一个显着的增殖是集成到设备和产品的尺寸变得更小。作为通孔(TSV)进行了研究,这不仅从减小包装尺寸,而且从缩短互连的距离,可以实现增强的信号传输的效果得到相当大的关注的这些功能要求,通过硅的结果。的TSV是通过堆叠式IC竖直孔,并且它们还负责在IC之间传递信号。因此,它们可以提高的信号转导的时间延迟,并允许比用引线键合技术堆叠式IC更好的电气性能。然而,文献的综述表明,电子元件会受到环境因素,如湿度,压力和温度容易受影响。一般而言,具有TSV结构的堆叠式IC通过比其他因素的温度变化是很容易受到影响,因为各材料具有不同的热膨胀。在最近,堆叠式IC封装已经主要涉及热 - 机械负荷比传统的单IC封装,这导致了一些问题,例如通过裂化,裂化管芯和界面剥离等。上述问题不仅影响设备的性能,而且还会导致器件失效。因此,大多数研究[1-9]的是注重与模拟方法讨论的热机械负荷。它们中的一些讨论TSV形状和应力[4,5]之间的关系。此外,大多数的人只建立本地TSV结构做他们的研究[4-9]。虽然它可以节省更多的时间,但它也增加了与实际情况误差百分比。和本文构建的三维四层堆叠式IC封装模型从谢[1]的文件,其中能够更接近真实情况。并设置STR-图片到从温度150℃至-50℃,这是因为退温度进行模拟。这是基于有限元理论,以减少使用时间,节约成本,如有限元模拟可以更快,更便宜比实验提供结果本文使用ANSYS软件。此外,该研究主要分析了硅通孔和微凸的最大von-Mises应力。此外,本文将挑选出的几何形状和底部填充的材料特性,这将严重影响通过试验设计(DOE)分析冯米塞斯应力值。通过美国能源部分析,关键因素被选择作为主要的设计因素,以减少冯米塞斯应力。这项研究可以提供显著的信息有效地设计产品,并提高可靠性。该信息还可以消除测试时间。

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