首页> 外文会议>International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems >A substructure method for strip level warpage simulation of a power module in assembly process
【24h】

A substructure method for strip level warpage simulation of a power module in assembly process

机译:组装过程中电源模块的条带级翘曲模拟的子结构方法

获取原文

摘要

A substructural method is developed to simulate the strip level warpage of a power module in assembly process. The comparison between substructure and non-substructure methods is presented and discussed. Parametric design of experimental (DoE) study on low side (LS) and high side (HS) die thickness, epoxy mold compound (EMC) thicknenss, as well the Young's modulus Ez of prepreg and Young's modulus of EMC is conducted in the simulation.
机译:开发了一种副结构方法来模拟组装过程中电源模块的条带级翘曲。提出和讨论了子结构和非子结构方法之间的比较。在低侧(LS)和高侧(HS)模具厚度上的实验(DOE)研究的参数化设计,环氧树脂化合物(EMC)厚度,以及EMC的预浸料和杨氏模量的杨氏模量EZ。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号