This paper proposes a technique to analyze distortion in analog CMOS integrated circuits. The proposed technique captures a transistor's nonlinearity using a two-dimensional Taylor series with coefficients that depend on the transconductance-to-current ratio (gm/ID) of a transistor. To explore the effectiveness of the proposed technique, a common-source amplifier is designed. The harmonics of the amplifier are calculated using both the gm/ID technique and Cadence's periodic steady state (PSS) analysis over a wide range of gm/ID. The results indicate a close match (i.e. a discrepancy less than 2 dB from gm/ID=8 to 30) and show that the proposed technique can indeed be incorporated in a gm/ID design flow.
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