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Dynamic Ternary Logic Gate Using Neuron-MOS Literal Circuit and Double Pass-Transistor Logic

机译:使用Neuron-MOS文字电路和双通晶体管逻辑的动态三元逻辑门

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A novel design scheme using neuron-MOS dynamic literal circuit and double pass-transistor logic (DPL), to realize voltage-mode dynamic ternary logic gate, is proposed. The double pass-transistor used to transmit ternary signal is controlled by the output of the dynamic literal circuit to realize ternary logic function. The complementarity and duality principles for generation of dynamic ternary complementary and dual circuits using double pass-transistor are also presented. The design results of dynamic ternary AND/NAND, OR/NOR, and mod-3 multiplication gate, demonstrate the effectiveness of the proposed scheme. The benefit of the proposed voltage-mode dynamic ternary gates is that they can be fabricated by standard CMOS process with a 2-ploy layer. Besides, they have simple and perfectly symmetrical structure. The effectiveness of the proposed dynamic ternary gates has been validated by HSPICE simulation results with TSMC 0.35μm 2-ploy 4-metal CMOS technology.
机译:提出了一种新颖的设计方案,采用神经元-MOM动态文字电路和双通晶体管逻辑(DPL)来实现电压模式动态三元逻辑门。用于传输三元信号的双通晶体管由动态文字电路的输出控制,以实现三元逻辑功能。还提出了使用双通晶体管产生动态三元互补和双电路的互补和二元原理。动态三元和/ NAND,或/ NOR和MOD-3乘法门的设计结果证明了所提出的方案的有效性。所提出的电压模式动态三元门的益处是它们可以通过标准CMOS工艺用2-PLOY层制造。此外,它们具有简单且完美的对称结构。通过HSPICE模拟结果验证了所提出的动态三元门的有效性,具有TSMC0.35μm2-PLOY 4-METAL CMOS技术。

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