Time resolved imaging solving FPGA logic fault localization by pattern matching technique

摘要

From a designer point of view, the analysis of a failure root cause can quickly become a nightmare if the number of hypothesis provided by a simulation tool is too high. To help solving this kind of problem the use of physical probing measurement can reduce drastically the number of assumptions made by the simulation by invalidating certain hypotheses. The purpose of this paper is to add to the simulation a new source of information based on light emission to solve this kind of problem. Virtual logic diagram computation is able to provide several hypotheses of fault for a given node and data coming from Time Resolved Imaging (TRI) measurement allows extraction of transition pattern for a given node where the assumption has been established. The cross-referencing of this information aims at eliminating wrong hypotheses and making the simulation more reliable.