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Prodn. of test pattern for identifying transit time faults in logic circuit

机译:产品逻辑电路中识别渡越时间故障的测试模式的设计

摘要

The gate plane is located between the input and output. the test path is divided in to at least two part test paths, to produce unambiguous "forking". Urgent necessary value applications are carried out directly for each part test path selected, for the spread of a signal value change. With each "forking" the hitherto test pattern prodn. status is stored. So that later in a further method step it can be recalled. If an output is reached, concluding signal value applications, not yet adjusted, are ensured by optional value allocations. Whilst a known back-track search method is used. With this, for different test path variants, which have common part test path, it avoids the compulsory carrying out of the urgent necessary multiple value applications.
机译:栅极平面位于输入和输出之间。测试路径至少分为两部分,以产生明确的“分叉”。对于所选的每个零件测试路径,都直接执行紧急必要值应用,以扩展信号值变化。对于每个“分叉”,迄今为止的测试模式都是这样。状态已存储。这样在以后的另一个方法步骤中就可以调用它。如果达到输出,则可以通过可选的值分配来确保尚未调整的最终信号值应用。同时使用已知的回溯搜索方法。这样,对于具有共同零件测试路径的不同测试路径变体,避免了必须执行的紧急必要的多值应用程序。

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