METHOD FOR IDENTIFYING UNTESTABLE FAULTS IN LOGIC CIRCUITS

摘要

A method of identifying untestable faults in a logic circuit. A lead inthe circuit is selected and the circuit is analyzed to determine which faults would beuntestable if the selected circuit lead were unable to assume a logic 0 and whichfaults would be untestable if the selected circuit lead were unable to assume a logic1. Faults that would be untestable in both (hypothetical) cases are identified asuntestable faults. Faults which would be untestable if the selected lead were unableto assume a given value may be determined based on an implication procedure. Theimplication procedure comprises the forward propagation of uncontrollabilityindicators and the backward propagation of unobservability indicators. Anuncontrollability indicator for the given value is assigned to the selected circuit leadand propagated forward through the circuit according to a set of well-definedpropagation rules. In addition, unobservability indicators are generated in the circuitbased on the propagation of uncontrollability indicators. These unobservabilityindicators are then propagated backward through the circuit. The (hypothetically)untestable faults are then determined based on the resultant indicators and theircorresponding circuit leads. Untestable faults may be identified in a sequentialcircuit by generating an equivalent combinational iterative array circuit model for afixed number of time frames. Faults that would be untestable in both (hypothetical)cases and which are located in the last (i.e., latest-in-time) time frame are identifiedas untestable faults.