The circuit testable realizations of multiple-valued functions are studied in this letter. First of all,it is shown that one vector detects all skew faults in multiplication modulo circuits or in addi-tion modulo circuits,and n+1 vectors detect all skew faults in the circuit realization of multiple-valued functions with n inputs. Secondly,min(max) bridging fault test sets with n+2 vectors are pre-sented for the circuit realizations of multiple-valued logic functions. Finally,a tree structure is used instead of cascade structure to reduce the delay in the circuit realization,it is shown that three vec-tors are sufficient to detect all single stuck-at faults in the tree structure realization of multiple-valued logic functions.
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