Impact of Through-Silicon-Via capacitance on high frequency supply noise in 3D-stacks

摘要

We analyze the bias and frequency dependent capacitance of the Power/Ground (P/G) Through-Silicon-Via (TSVs) and its impact on the high-frequency noise in the power delivery network (PDN) of a 3D stack. We show that the P/G TSVs in a 3D PDN act as on-chip distributed decoupling capacitances and hence, help reduce the high-frequency impedance. We present that for the same cross-sectional area, P/G TSVs created using a cluster of small diameter TSVs has higher capacitance than a single large diameter TSV and hence, can further reduce the high-frequency PDN impedance.