机译:利用睡眠模块的寄生电容的片上谐振电源噪声消除器,用于功率模式开关
the Dept. of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, 113-0033 Japan;
VLSI Design and Education Center (VDEC), The University of Tokyo, Tokyo, 113-0032 Japan;
Design Platform Development Division,Renesas Electronics Corporation, Kodaira-shi, 187-8588 Japan;
Design Platform Development Division,Renesas Electronics Corporation, Kodaira-shi, 187-8588 Japan;
VLSI Design and Education Center (VDEC), The University of Tokyo, Tokyo, 113-0032 Japan;
VLSI Design and Education Center (VDEC), The University of Tokyo, Tokyo, 113-0032 Japan;
power supply noise; resonance; parasitic capacitance; sleep block; dvs; power gating;
机译:睡眠模块的片内开关寄生电容器,用于降低谐振电源噪声
机译:混合信号堆叠式3-D-IC中片上开关模式电源的垂直噪声耦合
机译:片上总线开关电流建模及其对供电网噪声的影响
机译:利用具有三模功率门控结构的睡眠模块的开关寄生电容器来降低片上谐振电源噪声
机译:使用共形映射,有限差分时域和腔谐振器方法对片上和封装配电网络中的同时开关噪声建模。
机译:基于LLC谐振转换器的功率因数校正高压直流电源
机译:具有高压电源线的片上噪声消除器,用于纳秒级电源噪声