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On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch

机译:利用睡眠模块的寄生电容的片上谐振电源噪声消除器,用于功率模式开关

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摘要

This paper presents an on-chip resonant supply noise canceller utilizing parasitic capacitance of sleep blocks. The test chip was fabricated in a 0.18μm CMOS process and measurement results show 43.3% and 12.5% supply noise reduction on the abrupt supply voltage switching and the abrupt wake-up of a sleep block, respectively. The proposed method requires 1.5% area overhead for four 100k-gate blocks, which is 7. 1X noise reduction efficient comparing with the conventional decap for the same power supply noise, while achieves 47% improvement of settling time. These results make fast switching of power mode possible for dynamic voltage scaling and power gating.
机译:本文提出了一种利用睡眠模块寄生电容的片上谐振电源噪声消除器。该测试芯片采用0.18μmCMOS工艺制造,测量结果表明,在突然改变电源电压和突然唤醒睡眠模块时,电源噪声分别降低了43.3%和12.5%。所提出的方法需要四个100k门模块的1.5%的面积开销,即7。与相同功率下的传统decap相比,降噪效率达到1倍,而建立时间却缩短了47%。这些结果使快速切换功率模式成为可能,从而实现动态电压缩放和功率门控。

著录项

  • 来源
    《IEICE Transactions on Electronics》 |2011年第4期|p.511-519|共9页
  • 作者单位

    the Dept. of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, 113-0033 Japan;

    VLSI Design and Education Center (VDEC), The University of Tokyo, Tokyo, 113-0032 Japan;

    Design Platform Development Division,Renesas Electronics Corporation, Kodaira-shi, 187-8588 Japan;

    Design Platform Development Division,Renesas Electronics Corporation, Kodaira-shi, 187-8588 Japan;

    VLSI Design and Education Center (VDEC), The University of Tokyo, Tokyo, 113-0032 Japan;

    VLSI Design and Education Center (VDEC), The University of Tokyo, Tokyo, 113-0032 Japan;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    power supply noise; resonance; parasitic capacitance; sleep block; dvs; power gating;

    机译:电源噪声;谐振;寄生电容睡眠障碍dvs;电源门控;
  • 入库时间 2022-08-18 00:26:48

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