High-Speed Area-Efficient and Power-Aware Multiplier Design using Approximate Compressors along with Bottom-Up Tree Topology

摘要

Estimating arithmetic is a design paradigm for DSP hardware. By allowing structurally incomplete arithmetic circuits to occasionally perform imprecise calculations, higher performance can be achieved in many different electronic systems. By means of approximate compressor design and bottom-up tree topology, this paper presents a novel approach of implementing high-speed, area-efficient and poweraware multipliers. Experimental results are given to show the applicability and effectiveness of our proposed approach.