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Wallace tree multiplier array having an improved layout topology

机译:华莱士树乘法器阵列具有改进的布局拓扑

摘要

A Wallace tree multiplier array (40) performs multiply operations using operands received via a data path (42) having a predetermined height. Rows of carry save adders (CSAs 15'-19") add sets of partial products to generate sets of intermediate summands, which are recursively added to generate a set of final summands. A first group of CSAs form a column which is placed along an axis parallel to the data path (42), and are used to compute a more significant number of bits of each of the summands. The column height of the first group of CSAs is equal to and aligned with the height of the data path (42). A second group of CSAs are placed along an axis perpendicular to the column formed by the first group of CSAs, thereby minimizing the dimension of the multiplier along the data path. The second group of CSAs compute a less significant number of bits of the summands.
机译:华莱士树乘法器阵列(40)使用经由具有预定高度的数据路径(42)接收的操作数来执行乘法运算。行进位保存加法器(CSA 15'-19“)行添加部分乘积集以生成中间加总集,然后递归加总以生成最终加总集。第一组CSA形成一列,并沿着轴平行于数据路径(42),用于计算每个求和数的更多位数。第一组CSA的列高等于数据路径的高度(42) )。第二组CSA沿着垂直于第一组CSA形成的列的轴放置,从而最小化了乘数沿数据路径的尺寸。要求。

著录项

  • 公开/公告号US5265043A

    专利类型

  • 公开/公告日1993-11-23

    原文格式PDF

  • 申请/专利权人 MOTOROLA INC.;

    申请/专利号US19930009435

  • 申请日1993-01-27

  • 分类号G06F7/52;

  • 国家 US

  • 入库时间 2022-08-22 04:32:40

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