Parallel multiplier using skip array and modified wallace tree

摘要

A parallel multiplier by a skip array and a modified Wallace tree utilizes a modified Booth's encoder for encoding a multiplier according to a modified Booth's algorithm, a skip array for partial products, a modified wallace tree for adding binary bits, and a hybrid prefix adder for adding the final two lines. Fast multiplication of 0 (log n) is continuously performed without a standby state of a carry output and the regularity of the arrangement of the parallel multiplier is improved so that its chip area and manufacturing cost are reduced.