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High-Speed Area-Efficient and Power-Aware Multiplier Design using Approximate Compressors along with Bottom-Up Tree Topology

机译:使用近似压缩机和自下而上的树形拓扑结构的高速高效面积和功耗感知乘法器设计

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Estimating arithmetic is a design paradigm for DSP hardware. By allowing structurally incomplete arithmetic circuits to occasionally perform imprecise calculations, higher performance can be achieved in many different electronic systems. By means of approximate compressor design and bottom-up tree topology, this paper presents a novel approach of implementing high-speed, area-efficient and power-aware multipliers. Experimental results are given to show the applicability and effectiveness of our proposed approach.
机译:估计算法是DSP硬件的设计范例。通过允许结构不完整的算术电路偶尔执行不精确的计算,可以在许多不同的电子系统中实现更高的性能。通过近似的压缩机设计和自下而上的树形拓扑,本文提出了一种新颖的方法来实现高速,面积有效和功耗感知的乘法器。实验结果表明了该方法的适用性和有效性。

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