HIGH-SPEED MULTIPLIER, REALIZED IN SMALL SIZE SO AS TO BE USED AS A MULTIPLIER ENGINE OF A PROCESSOR AND DESIGNED IN SINGLE STRUCTURE HAVING REGULARITY

摘要

PURPOSE: A high-speed multiplier is provided to carry out a high-speed multiplication by comprising a data parser, a 9x9 multiply cluster, an add-path, and pipelines, thereby being used in mega library type for a high-speed graphic processor or a multimedia processor. CONSTITUTION: A data parser(1) separates input data in byte unit, expands sign/zero parts, and stores the expanded parts in a register. The first end pipeline(2) pipelines values of a data bus through registers 'p' and 'c', and transmits an 'Msize' value and an 'fUNC_sel' value to a next end. A matrix multiplier(3) comprises two repairing multipliers, receives an output value of the register to perform a multiplication in simple byte unit, and generates a partial multiplication output. The second end pipeline(4) consists of a register 'm' for storing the partial multiplication results and a register 'p' for overpassing the stored 'Msize' value and the 'fUNC_sel' value to a next end. A partial adder(5) expands a code bit and a zero bit to shift the expanded bits, and adds the shifted bits together to output a final result.