A Study of Barrier Engineered Al_2O_3 and HfO_2 High-K Charge Trapping Devices (BE-MAONOS and BE-MHONOS) with Optimal High-K Thickness

摘要

The behavior of barrier engineered charge trapping devices incorporating Al_2O_3 and HfO_2 high-K layers has been critically examined. We propose to use a thicker buffer oxide (> 6 nm) and thin (<5nm) high-K top capping layer for BE-MAONOS and BE-MHONOS in order to improve the reliability. Thinner high-K top capping layer reduces the fast initial charge loss under high-temperature baking. Moreover, it also reduces the undesired transient read current relaxation. These effects are due to the bulk trapped charge in high-K material during programming/erasing. By reducing the high-K thickness these reliability issues can be minimized. We also found that HfO_2 has a better thickness scaling capability than Al_2O_3. Finally, a high-performance BE-SHONOS (with n~+-poly gate and HfO_2 top capping layer) transistor is demonstrated in this work.