PLL lock time prediction and parametric testing by lock waveform characterization

摘要

Phase Locked Loop (PLL) testing is complicated due to its mixed signal nature. Internal nodes, which are digital as well as analog, are sensitive to phase, delays and parasitic loads. Parametric characteristics such as lock time, jitter, phase etc. may be critical for a PLL depending on the application and comprehensive production testing of any of these parameters is impractical due to test cost implications. This paper proposes a method to sample and analyze the PLL lock waveform in order to predict the PLL lock time and perform parametric testing of the internal analog blocks. Data is presented across process corners to support the proposal. This method uses either an Automatic Test Equipment (ATE) or on-chip Digital Signal Processor (DSP) to compute FFT values for the lock waveform which is then used for lock time prediction. The test scheme includes parametric fault coverage in addition to catastrophic fault coverage without any significant test time overhead.