首页> 外文会议>Proceedings of 2008 international conference on electronic packaging technology high density packaging (ICEPT-HDP 2008) >Warpage Reduction of Package-on-Package (PoP) Module by Material Selection Process Optimization
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Warpage Reduction of Package-on-Package (PoP) Module by Material Selection Process Optimization

机译:通过材料选择和工艺优化来减少层叠封装(PoP)模块的翘曲

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The package technology has matured significantly over the past several years, shifting from conventional components and direct board level assembly to chip or package level system integration. Two major commonly used approaches are System-on-Chip (SoC) and System-in-Package (SiP).Package-on-Package (PoP) that integrates logic die in the bottom package and memory die in the top package into a single 3D package is one of the promising SiP solutions. The major advantage of PoP packaging is that the top and bottom packages, which are usually designed with FBGA and PBGA package formats, can be tested individually before they are assembled. The yield loss of the whole PoP module can be reduced significantly. However, due to the Coefficient of Thermal Expansion (CTE) mismatch and the stiffness mismatch exist among EMC, substrate and silicon chip, warpages on both top and bottom packages are often observed. Large warpage could cause solder joint open failure and substrate delamination, leading to the electrical connection failure of the assembled module. Theoretically, three approaches can be used to solve the warpage issue of two BGA packages contained in a PoP module: package design, material selection and process optimization. Developing a new package or changing the existing design usually involves many efforts and needs long cycle time, which can not meet the needs of competitive microelectronics industry. The material selection and process optimization are often adopted by industry to achieve the goal of shortening time to market. In this paper, Finite Element (FE) simulation is performed firstly. The CTE of epoxy molding compound (EMC) is found to make an important contribution to the warpage of PoP. The guideline for materials selection is proposed. Based on this guideline, one type of "Green" EMC is selected. Material properties of EMC including filler content, curing degree, CTE and Tg are characterized with thermo-gravimetric analysis (TGA), differential scanning calorimetry (DSC) and thermo-mechanical analysis (TMA) respectively. The effect of the material properties and the post mold curing (PMC) process on the warpage behavior of employed to characterize the warpage of the molded block and signal units.
机译:在过去的几年中,封装技术已经显着成熟,从传统的组件和直接的板级组装转向芯片或封装级的系统集成。两种主要的常用方法是片上系统(SoC)和片上系统(SiP)。片上封装(PoP)将底部封装中的逻辑芯片和顶部封装中的内存芯片集成到一个封装中3D封装是有前途的SiP解决方案之一。 PoP封装的主要优势在于,通常采用FBGA和PBGA封装格式设计的顶部和底部封装,可以在组装之前进行单独测试。整个PoP模块的成品率损失可以大大降低。但是,由于EMC,基板和硅芯片之间存在热膨胀系数(CTE)不匹配和刚度不匹配,因此经常会在顶部和底部封装上观察到翘曲。较大的翘曲可能会导致焊点断开故障和基板分层,从而导致组装模块的电气连接故障。从理论上讲,可以使用三种方法来解决PoP模块中包含的两个BGA封装的翘曲问题:封装设计,材料选择和工艺优化。开发新封装或更改现有设计通常需要付出很多努力,并且需要较长的周期时间,无法满足竞争激烈的微电子行业的需求。工业界通常采用材料选择和工艺优化来达到缩短产品上市时间的目的。本文首先进行了有限元仿真。发现环氧模塑化合物(EMC)的CTE对PoP的翘曲起重要作用。提出了材料选择指南。根据此准则,选择了一种“绿色” EMC。分别通过热重分析(TGA),差示扫描量热法(DSC)和热机械分析(TMA)表征EMC的材料性能,包括填料含量,固化度,CTE和Tg。材料性能和模后固化(PMC)工艺对所采用的翘曲行为的影响用来表征模制块和信号单元的翘曲。

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