LOW STRESS POLISHING OF COPPER/LOW-K DIELECTRIC STRUCTURES

摘要

The rapid miniaturization of the CMOS devices, combined with the introduction of fragile interconnects materials such as copper and low K dielectrics, have increased the need for use of low mechanical stress CMP techniques. Conventional slurries based on hard abrasive particles may not be an optimal choice for polishing of next generation copper /low K dielectric structures. This article details some of the critical stress issues during CMP polishing of interconnect structures.