Taming noise in deep submicron digital integrated circuits (panel)

摘要

As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of digital VLSI chips. Are functional failures due to noise really a problem in a static CMOS design? Are design rules in the circuits and interconnect sufficient to protect against noise failures? Do design rules targetted to ensure noise immunity result in excessive penalty to performance and area due to their inherent conservatism? Is inductance in the interconnect really a problem? How much do we really need to account for capacitive coupling inductance, and inductive coupling in delay analysis?