Noise estimation for coupled RC interconnects in deep submicron integrated circuits

摘要

Noise estimation for coupled interconnects in deep submicron integrated circuits. One aspect of the invention is a method for interconnect coupling noise estimation. Another aspect of the invention is a computer readable medium embodying computer program code. The computer program code is configured to cause a computer to perform steps for estimating the interconnect coupling noise. The interconnect coupling noise estimation (hereafter noise estimation) includes modeling a circuit. The circuit includes a pair of interconnects, each interconnect connecting a driver gate to a load gate, where signal activity at a first interconnect of the pair of interconnects is having an impact on a second interconnect of the pair of interconnects. The circuit modeling includes modeling the first and second interconnects, driver gates, and load gates. Driver gates are modeled using a voltage source driving a resistance. Load gates are modeled using a capacitance. The noise estimation further includes expressing transfer characteristics of the modeled circuit for one of or, each one at a time, for a plurality of input voltages including step and ramp input voltages. Additionally, the noise estimation includes expressing a voltage at the second interconnect based on the transfer characteristics. The transfer characteristics are expressed in view of a capacitive coupling between the first and second interconnects. The voltage represents the impact on the second interconnect that is in the form of interconnect coupling noise. The noise estimation also includes determining a peak value of the interconnect coupling noise from the expression for the voltage at the second interconnect. The interconnect coupling noise reaches a peak at a time determined for one of or, each one at a time, for both of the step and ramp input voltages.