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System and method for topology based noise estimation of submicron integrated circuit designs
System and method for topology based noise estimation of submicron integrated circuit designs
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机译:基于拓扑的亚微米集成电路设计噪声估计的系统和方法
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摘要
A tool for computing noise coupled onto victim lines from aggressor lines of an integrated circuit has code for traversing a victim line of the integrated circuit layout to measure its length, its average width, a coupling length, and a harmonic mean of spacing between the victim line and aggressor lines. The tool has code for computing a resistance, estimated coupling capacitance, and total capacitance of the victim line from these parameters.
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