Vertical slit transistor based integrated circuits (VeSTICs) paradigm

摘要

In this presentation new, unorthodox (i.e. ITRS incompatible), IC design/manufacturing paradigm is proposed. This paradigm has been conceived as a response to the rapidly growing complexity and increasing number of stumbling blocks posed by the nano-scale IC era. It has been constructed using notion of a strict layout regularity imposed on IC layout. Such restriction is seen as a remedy for dramatic increase of litho cost and complexity expected to be major issues for the "below-32-nm" products. Such regularity has been discussed in the past for IC interconnects. Focus of this talk is on active devices. The central element of the proposed vision is Vertical Slit Field Effect Transistor (VeSFET). It is shown that Vertical Slit Transistor based integrated circuits (VeSTICs) may enable much denser, much easier to design, test and manufacure, as well as, easily 3D-extendable and OPC-free ICs. The proposed paradigm has been developed assuming that it must reuse CMOS-based desig/manufdacturing infrasrtuctur and expertise that does exist today.