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Bipolar vertical transistors in monolithic integrated circuit - are made using dopant masks for forming base and transistor zones

机译:单片集成电路中的双极垂直晶体管-使用掺杂剂掩模制成以形成基极和晶体管区域

摘要

A monocrystalline semiconductor substrate is coated with a layer of an inorganic insulating material contg. dopant windows so dopant masks are obtd. for forming a base zone and a transistor zone which surrounds the former zone (B). Windows have a rectangular shape, and form two dopant masks where at least some of the rectangular exposed zones of the substrate have the same side dimension. One pref. process uses a mask of SiO2 with dopant windows which can be partly covered by a layer of siO2 which is subsequently removed, i.e. so windows of different area can be employed in a sequence of doping operation. Used in the mfr. of integrated injection logic or merged transistor logic circuits with a space saving of e.g. 60% w.r.t. conventional devices.
机译:单晶半导体衬底涂覆有一层无机绝缘材料contg。掺杂剂窗口,因此不能使用掺杂剂掩模。用于形成基极区和围绕前者区(B)的晶体管区。窗口具有矩形形状,并形成两个掺杂剂掩模,其中衬底的至少一些矩形暴露区域具有相同的侧面尺寸。一首该方法使用具有掺杂剂窗口的SiO 2掩模,该掩模可以部分地被随后除去的SiO 2层覆盖,即,因此可以在一系列掺杂操作中采用不同面积的窗口。用于mfr。集成的注入逻辑电路或合并的晶体管逻辑电路可节省空间,例如w.r.t. 60%常规设备。

著录项

  • 公开/公告号DE2804525A1

    专利类型

  • 公开/公告日1979-08-16

    原文格式PDF

  • 申请/专利权人 SIEMENS AG;

    申请/专利号DE19782804525

  • 发明设计人 WERNERWOLFGANGDR.;

    申请日1978-02-02

  • 分类号H01L29/72;H01L27/04;

  • 国家 DE

  • 入库时间 2022-08-22 19:46:54

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