A Back - Biased 0.65 ¿m Leffn CMOS EEPROM Technology For Next - Generation Sub 7 ns Programmable Logic Devices

摘要

A high-speed back-biased CMOS EEPROM technology and its application to Programmable Logic Devices (PLDs) will be described. Several key features have allowed the fabrication of a next generation high performance EECMOS PLD; the use of two independent families of transistors for the high voltage programming and read paths, the application of back-bias and careful optimisation of a double-polysilicon EEPROM cell. A sub 7 ns EECMOS PLD is described.