Characterization of Vt instability in hafnium based dielectrics by pulse gate voltage techniques CMOS device applications

摘要

The transient threshold voltage instabilities occurring in CMOS devices in high-k oxide are considered as one of the major reliability issues opposing their successful integration. In this paper, we present an improved pulsed gate voltage technique for the characterization and the physical analysis of these phenomena. Based on the experimental observations of the trapping and detrapping kinetics, we determine the underlying physical mechanism and develop a new approach enabling the extraction of the energy distribution of the traps, aiming at the physical interpretation of their origin.