A Novel Low Power Interface Circuit Design Technique for Multiple Voltage Islands Scheme

摘要

Power has become an important concern for nanometer circuit design as well as timing characteristic. In this paper, a novel low power interface circuit design technique was proposed for multiple voltage islands scheme by using output feedback, conditional switch, and pulsed clock technique. The method was applied to new types of flip-flops and combinational logics to eliminate level converters and remove redundant switching activities. Combined with multiple VTH technique, a low clock swing flip-flop is designed to verify our new method. Experimental results show that the leakage power of the new flip-flop can be reduced by an average of 58.14% in standby mode and the total power consumption can be reduced by an average of 55.76% in active mode, while the delay time stays the same