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Effective on-chip inductance modeling for multiple signal lines and application on repeater insertion

机译:针对多条信号线的有效片上电感建模以及在中继器插入中的应用

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A new approach to handle the inductance effect on multiple signal lines is presented. The worst case switching pattern is first identified. Then a numerical approach is used to model the effective loop inductance (L/sub eff/) for multiple lines. Based on look-up table for L/sub eff/, an equivalent single line model can be generated to decouple a specific signal line from the others to perform static timing analysis. Compared to the use of full RLC netlist for multiple lines, this approach greatly improves the computation efficiency and maintains accuracy for timing and signal integrity analysis. Applications to repeater insertion in the critical path chains are demonstrated. For a single line, the RLC model minimizes delay with fewer number of repeaters than RC model. However, for multiple lines, we find that same number of repeaters is inserted for optimal delay according to both the RC and RLC multiple line models.
机译:提出了一种处理多条信号线上的电感效应的新方法。首先确定最坏情况的切换模式。然后,采用数值方法对多条线路的有效环路电感(L / sub eff /)进行建模。基于L / sub eff /的查找表,可以生成等效的单线模型以将特定信号线与其他信号线解耦,以执行静态时序分析。与在多条线路上使用完整的RLC网表相比,该方法大大提高了计算效率,并保持了定时和信号完整性分析的准确性。演示了将中继器插入关键路径链的应用。对于单条线路,RLC模型比RC模型具有更少的中继器数量,从而最大程度地减少了延迟。但是,对于多条线路,我们发现根据RC和RLC多线路模型,插入了相同数量的中继器以获得最佳延迟。

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