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Depletion and enhancement mode InP high electron mobility transistors fabricated by a dry gate recess process

机译:通过干栅凹槽工艺制造的耗尽型和增强型InP高电子迁移率晶体管

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We report depletion and enhancement mode InP high electron mobility transistors (HEMTs) fabricated using CH/sub 4//H/sub 2/ selective dry etch gate recess process. Under the etching conditions developed, the process has a In/sub 0.7/Ga/sub 0.3/As to In/sub 0.52/Al/sub 0.48/As selectivity of 130. The dc threshold voltages of the devices fabricated in this way increase from -1.3 V to 0.1 V as a function of dry etch time, with an extrinsic transconductance of 520 mS/mm in the depletion mode and 800 mS/mm in enhancement mode. The devices exhibit an extrapolated cut-off frequencies of 150 GHz. This work demonstrates the potential of the use of dry etching as a gate recess technology for the future development of high frequency InP-based circuits.
机译:我们报告了使用CH / SUB 4 // H / SUB 2 /选择性干蚀刻栅极凹陷工艺制造的耗尽和增强模式INP高电子迁移率晶体管(HEMT)。在开发的蚀刻条件下,该方法具有In / Sub 0.7 / Ga / sub 0.3 /至/ sub 0.52 / Al / sub 0.48 /选择性为130.以这种方式制造的器件的DC阈值电压增加-1.3 V至0.1V作为干蚀刻时间的函数,在耗尽模式下具有520ms / mm的外部跨导和增强模式的800ms / mm。该装置表现出150GHz的外推截止频率。这项工作展示了使用干蚀刻作为栅极凹陷技术的潜力,以实现高频INP基电路的未来发展。

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