An effective method for obtaining interface trap distribution in MOS capacitors with tunneling gate oxides

摘要

A novel and effective method for obtaining interface trap distribution at the Si/SiO/sub 2/ interface is presented and has been applied to investigate stress-induced interface trap generation in ultrathin oxide MOS capacitors. By a critical analysis of bipolar voltage pulse induced currents through the MOS capacitors, a technique is developed to determine the energy distribution of interface traps. A remarkable feature of the method is that it does not require the knowledge of surface potential and doping profile curves and is free from any approximations that are usually made in existing capacitance-voltage methods. The proposed technique is a reliable tool for quantitative characterization of process- and stress-induced interface trap generation in ultrathin oxide MOS structures.