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A new vertically stacked poly-Si MOSFET with partially depleted SOI operation for densely integrated SoC applications

机译:一种新型的垂直堆叠式多晶硅MOSFET,具有部分耗尽的SOI操作,适用于密集集成的SoC应用

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Vertical transistors take up less area than conventional planar CMOS devices and are thus promising as a means for increased densities of integration. Most of the vertical MOSFET structures proposed so far, however, require sophisticated processing which is incompatible with conventional CMOS processes. In this paper, we propose the use of a vertical poly-Si pMOSFET for SoC applications; this structure is easily stacked on bulk nMOS, eliminating the need for an n-well region and significantly reducing chip Size. The formation of poly-Si grain boundaries across the active channels of poly-Si MOSFETs means that these devices tend to exhibit poor performance in the form of large threshold-voltage fluctuations and large subthreshold swings. A vertical poly-Si transistor that operates with a partially depleted SOI structure and shows excellent DC characteristics has been developed as a solution to these problems. The impact of this new vertical pMOS structure on 6T-SRAM is also demonstrated.
机译:垂直晶体管所占面积比常规平面CMOS器件要小,因此有望成为增加集成密度的一种手段。然而,迄今为止提出的大多数垂直MOSFET结构需要复杂的处理,这与传统的CMOS工艺不兼容。在本文中,我们建议在SoC应用中使用垂直多晶硅pMOSFET。这种结构很容易堆叠在体nMOS上,从而无需n阱区域,并显着减小了芯片尺寸。在多晶硅MOSFET的有源沟道上形成多晶硅晶界意味着这些器件往往会以较大的阈值电压波动和较大的亚阈值摆幅形式表现出较差的性能。为了解决这些问题,已经开发出以部分耗尽的SOI结构工作并显示出优异的DC特性的垂直多晶硅晶体管。还展示了这种新型垂直pMOS结构对6T-SRAM的影响。

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