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New planar self-aligned double-gate fully-depleted P-MOSFETs using epitaxial lateral overgrowth (ELO) and selectively grown source/drain (S/D)

机译:利用外延横向过生长(ELO)和选择性生长的源极/漏极(S / D)的新型平面自对准双栅极全耗尽P-MOSFET

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Simulations have shown that self-aligned double-gate SOI MOSFETs are able to eliminate short channel effects and increase circuit performance for devices down to the L/spl sim/20-30 nm regime (Frank et al., 1992; Wong et al., 1994 and 1998; Fossum et al., 1998). Planar self-aligned fully-depleted double-gate structures are considered most promising (Wong et al., 1997). However, previous proposed fabrication processes have not shown experimental data with low subthreshold slopes or off-currents (Lee et al., 1999). This work presents, for the first time, successfully fabricated planar self-aligned double-gate P-MOSFETs with a good subthreshold swing (>70 mV/dec) and low leakage current (I/sub off/>0.3 pA//spl mu/m) using epitaxial lateral overgrowth (ELO). It also has a unique selective epitaxially grown source/drain (S/D). The measured hole mobility, 215 cm/sup 2//V-s at V/sub GS/-V/sub T/=-0.6 V, shows the good channel and interface quality obtained by using ELO.
机译:仿真表明,自对准双栅SOI MOSFET能够消除短沟道效应并提高低至L / spl sim / 20-30 nm制程的器件的电路性能(Frank等,1992; Wong等。 (1994和1998; Fossum等,1998)。平面自对准全耗尽双栅结构被认为是最有前途的(Wong等,1997)。但是,先前提出的制造工艺尚未显示出具有低亚阈值斜率或截止电流的实验数据(Lee等,1999)。这项工作首次展示了成功制造的平面自对准双栅极P-MOSFET,具有良好的亚阈值摆幅(> 70 mV / dec)和低泄漏电流(I / sub off /> 0.3 pA // spl mu / m)。它还具有独特的选择性外延生长的源极/漏极(S / D)。在V / sub GS / -V / sub T / =-0.6 V时测得的空穴迁移率215 cm / sup 2 // V-s显示了使用ELO获得的良好通道和界面质量。

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