In this paper, a numerical model for flip-chips in electronic packaging is constructed referring to existing experimental observation. The finite element (FE) simulation of interfacial crack propagation has been carried out along the interface between underfill and silicon chip without crack and with an initial crack, and the symmetric Galerkin multi-zone boundary element (BE) analysis has been also developed to calculate the same models as FE ones. In FE simulation, a critical stress criterion is adopted as the fracture criterion for the crack propagation. The normal and shear stress distributions along the interface are obtained from numerical analyses. The relation of load line deflection and crack length, and energy release rate vs. crack extension curve are also calculated from numerical results. On the other hand, the thermal stress field resulting from the difference of the coefficient of thermal expansions (CTEs) for different layer materials is investigated by increasing temperature from 20/spl square/ to 100/spl square/. FE results indicate that stress concentration occurs near the interface between underfill and silicon chip. Numerical results from FE and BE analyses show to be in good agreement with experiment ones.
展开▼
