New approach for the extraction of gate voltage dependent series resistance and channel length reduction in CMOS transistors

摘要

The resistance based extraction method for the determination of effective channel length and series resistance behaviour with gate bias is critically analysed. The impossibility of extracting the gate voltage variations of these parameters concurrently is demonstrated. Then a new parameter extraction procedure is given and experimentally applied to a wide range of technologies, from 1.2 /spl mu/m down to 0.1 /spl mu/m. Finally, the lack of resolution in the determination of channel length reduction and series resistance when the effective gate bias tends to zero and the impact of the substrate gate bias on these parameters is studied in detail.