A methodology to reduce the computational cost of behavioral test pattern generation

摘要

The authors present different methods of computing testability measures for behavioral descriptions of digital circuits. The computation of testability measures based on the work described has been implemented and integrated into a behavioral deterministic test pattern generator to study the effectiveness of the proposed testability measures. The internal model derived from behavioral descriptions is presented. The main features of a behavioral test pattern generation algorithm that was implemented are described. The definition of controllability and observability of the basic elements of the internal model is given. Experiments performed on test generation are described, and the results are summarized.