首页> 外文会议>IPC Electronic Circuits World Convention, Printed Circuits Expo, Apex, and the Designers Summit 2005(ECWC 10): The Perfect Fit vol.4 >Test Equipment for CMOS Lead Open Detection Based on Supply Current under AC Electric Field Application
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Test Equipment for CMOS Lead Open Detection Based on Supply Current under AC Electric Field Application

机译:交流电场下基于电源电流的CMOS引线开路检测测试设备

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Open leads have often occurred in logic circuits implemented on printed circuit boards with the state-of-art technology. We proposed an electrical test method to detect them with high fault coverage. The test method is based on supply current change of a circuit under test that is caused with AC electric field supplied from the outside of the circuit. In this paper, we propose a test equipment for the test method. A voltage signal that is obtained by mixing a rectangle waveform signal and a sine waveform one is supplied between electrodes to generate the electric field. Amplitude of the signal continues to increase in proportion to time during a specified time. When supply current change that is larger than a threshold value appears, it stops increasing the amplitude and it is concluded that open leads occur in the circuit. If the supply current change does not appear within the specified time, it is concluded that no open leads occur in the circuit. In this paper, it is shown experimentally that an open lead at a CPLD of PLCC package is detected with the test equipment.
机译:在采用最新技术的印刷电路板上实现的逻辑电路中,经常会出现断路。我们提出了一种电气测试方法来检测具有较高故障覆盖率的故障。该测试方法基于被测电路的电源电流变化,该变化是由电路外部提供的交流电场引起的。在本文中,我们提出了一种用于测试方法的测试设备。在电极之间提供通过将矩形波形信号和正弦波形混合而获得的电压信号以产生电场。在指定时间内,信号的幅度与时间成比例地持续增加。当出现大于阈值的电源电流变化时,它将停止增加幅度,并得出电路中出现断路的结论。如果在指定时间内电源电流没有出现变化,则可以得出结论,电路中没有断路。本文通过实验表明,使用测试设备可以检测到PLCC封装的CPLD处的开路引线。

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