首页> 外文会议>International Conference on Silicon Carbide and Related Materials; 20050918-23; Pittsburgh,PA(US) >Reduction of Defects in GaN Epitaxial Films Grown Heteroepitaxially on SiC
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Reduction of Defects in GaN Epitaxial Films Grown Heteroepitaxially on SiC

机译:减少在SiC上异质外延生长的GaN外延膜中的缺陷

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Silicon carbide (SiC) has become the substrate of choice for III-N epilayers applied to electronic devices due to the lack of a native III-N substrate. This is particularly true for high power applications, since the thermal conductivity of the substrate enhances device performance. Although the GaN lattice match is slightly better for SiC than for sapphire, the dislocation densities that result are still very high (generally in the high 10~8 cm~(-2) range) and often deleterious to device performance. Screw-component dislocations are especially critical since they serve as leakage paths in vertically conducting III-N devices. In this paper efforts to reduce the extended defect density in III-N films grown on SiC will be reviewed. Details on recent efforts to use step-free SiC mesa surfaces arrayed on commercial 4H-SiC substrates will then be highlighted showing dramatic reductions in extended defect densities and the virtual elimination of critical defects for vertically conducting devices. In these experiments, SiC surfaces that are homoepitaxially grown step-free or of very low step density have been used as growth templates for thin ( < 3 μm) GaN films deposited on a novel 1000 A AlN nucleation layer characterized by a total dislocation density two orders of magnitude lower than the previous state-of-the-art, and with no evidence of screw-component dislocations.
机译:由于缺少天然的III-N衬底,碳化硅(SiC)已成为应用于电子设备的III-N外延层的首选衬底。对于高功率应用而言尤其如此,因为基板的导热性提高了器件性能。尽管SiC的GaN晶格匹配略好于蓝宝石,但所产生的位错密度仍然很高(通常在10〜8 cm〜(-2)的高范围内),并且通常对器件性能有害。螺丝组件的错位特别重要,因为它们在垂直传导的III-N器件中充当泄漏路径。在本文中,将对减少在SiC上生长的III-N膜中扩展缺陷密度的努力进行综述。然后将重点介绍最近使用在商用4H-SiC衬底上排列的无台阶SiC台面表面的努力的详细信息,显示出扩展缺陷密度的显着降低以及垂直导电器件的关键缺陷的虚拟消除。在这些实验中,均采用无外延无步或非常低的步距密度生长的SiC表面作为沉积在新型1000 A AlN成核层上的GaN薄膜(<3μm)的生长模板,其特征在于总位错密度为2比以前的最新技术低几个数量级,并且没有丝杠组件错位的迹象。

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