Low noise active loop filter for radar PLL applications

摘要

This paper presents a simple structure for a low noise active loop filter, designed in 28nm CMOS process. Design strategies are used for minimizing both thermal and flicker noise at critical frequencies around 1MHz for radar PLL applications. Results show an input referred noise of 2.81 nV/VHz @1MHz for the op-amp of the loop filter, with nominal conditions and 1.8 V power supply, occupying an area of 0.039mm