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Area-efficient PLL with a low-noise low-power loop filter

机译:具有低噪声,低功耗环路滤波器的面积有效的PLL

摘要

Techniques for reducing noise and power consumption in a loop filter for a phase-locked loop (PLL) are described herein. In one embodiment, a loop filter for a PLL comprises a first proportional capacitor, a second proportional capacitor, an active device, and a plurality of switches. The plurality of switches are configured to alternately couple the first proportional capacitor and the second proportional capacitor to a first charge pump, to alternately couple noise from the active device to the first proportional capacitor and the second proportional capacitor, and to alternately couple the first proportional capacitor and the second proportional capacitor into a feedback circuit, wherein the feedback circuit produces an output voltage of the loop filter.
机译:本文描述了用于减少锁相环(PLL)的环路滤波器中的噪声和功耗的技术。在一个实施例中,用于PLL的环路滤波器包括第一比例电容器,第二比例电容器,有源器件和多个开关。多个开关被配置为将第一比例电容器和第二比例电容器交替耦合至第一电荷泵,以将噪声从有源器件交替耦合至第一比例电容器和第二比例电容器,并交替耦合第一比例电容器和第二比例电容器。电容器和第二比例电容器分成反馈电路,其中该反馈电路产生环路滤波器的输出电压。

著录项

  • 公开/公告号US9024684B2

    专利类型

  • 公开/公告日2015-05-05

    原文格式PDF

  • 申请/专利权人 QUALCOMM INCORPORATED;

    申请/专利号US201313831639

  • 发明设计人 YU SONG;NAN CHEN;

    申请日2013-03-15

  • 分类号H03B1/00;H03K5/00;H04B1/10;H03L7/08;H03L7/087;H03L7/089;H03L7/093;

  • 国家 US

  • 入库时间 2022-08-21 15:17:11

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