A High-Performance PLL With a Low-Power Active Switched-Capacitor Loop Filter

摘要

A 2.5-GHz phase-locked loop (PLL) employing a low-power active switched-capacitor loop filter is presented. A subthreshold inverter-based active loop filter is presented and analyzed. Advantages such as type-II loop dynamics, low reference spurs, and small on-chip capacitors are achieved. In addition, 1/f noise of the inverter amplifier can be suppressed by the filter's auto-zeroing operation. The prototype is designed and fabricated in a 0.18- $muhbox{m}$ CMOS technology. Measurement results show phase noise of $-$86 dBc/Hz at a 100-kHz offset, $-$124.0 dBc/Hz at a 3-MHz offset, and a reference spur level of $-$64 dBc. The PLL consumes about 16 mW with 0.46 mW dedicated to the loop filter active components.