TCAD simulation for low power UTBB FDSOI CMOS device

摘要

In this work a UTBB FDSOI model has been proposed by which leakage current is drastically reduced. Therefore it gives us freedom to scale down the device. Various comments on Sub-threshold slope (SS) and threshold voltage have been made. Effect of Buried Oxide (BOX) and Channel length variation has been described in terms of on-state current, off-state current, threshold voltage and SS. AC analysis of CMOS device has also been done by simulating the basic capacitance of proposed device. This model is highly appreciated for low power while using with multi threshold voltage.