Mechanical Reliability of Cu/Low-k Multi-Layer Interconnects in Flip Chip Packages

摘要

The impact of Chip Package Interaction (CPI) on the mechanical reliability of Cu/Ultra low-k interconnects in a flip chip package was investigated using 3D Finite Element Analysis (FEA). A modified virtual crack closure technique (MVCC) was applied to calculate energy release rate (ERR) at critical interfaces. To calculate ERR at the interface in a Cu/low-k structure,four step sub-modeling approach was used to link the deformation from the package level to the interconnect revel. The simulation was focused on die attach process for Pb-free process before underfilling where the maximum CPI effect is expected. The CPI was first analyzed at the interfaces in two metal-layer interconnects. The ERR was found to increase rapidly when the modulus of dielectric materials become lower than 10GPa. In contrast,the effect of coefficient of thermal expansion (CTE) of dielectric material on ERR was found to be small. Then,the CPI for a four metal-layer structure was investigated. The ERR at the interface for upper M3 and M4 levels were consistently higher than those of lower M1 and M2 levels. The M4 interface show 2.5 times higher ERR than the lower levels when the same low-k material is used for all layers. However,when TEOS is used in the M4 level,the ERR at M3 interface becomes 35% higher than the M4 level. Finally,the ERR was found to increase by imposing the residual stresses generated during the processes before packaging indicating that the temperature during the process need to be optimized to control CPI.