A >3GHz ERBW 1.1GS/S 8B Two-Sten SAR ADC with Recursive-Weight DAC

摘要

This work presents an 8b two-step SAR ADC for GS/s single-channel operations. A recursive-weight DAC topology is proposed in the 2nd stage with minimized capacitors and simple control logic. A partially-dual-plate sampling technique is exploited to relax the restraints of comparators and reduce the total amount of capacitors. Prototyped in a 40-nm CMOS process, this ADC occupies only 22×75 μm