New fully-differential amplifier-less pipelined ADC with wide power scalability and ERBW

摘要

A new fully-differential energy-efficient amplifier-less technique for pipelined analog-to-digital converter (ADC) suitable for video signal conversion is presented in this paper. It employs a capacitive charge pump and a comparator-controlled charging buffer to realize the residue amplification. The circuit is differential and the common-mode input is rejected at the output, although no active common-mode feedback circuit is used. In principle, this technique eliminates static power consumption in the residue amplification process, leaving only the necessary dynamic power consumption, which is directly scalable to the sampling rate (f_s) like in a digital circuit. A prototype ADC was fabricated in a 1.8 V 0.18 μm CMOS technology. It consumes 54 μW at 125 kS/s and 4.94 mW at 25 MS/s while measuring a signal-to-noise-plus-distortion ratio of 52 dB, independent of f_s. Furthermore, enabled by a built-in passive sample-and-hold, the ADC achieves a 36 MHz effective resolution bandwidth at 25 MS/s.