A 2.3-MW, 950-MHz, 8-Bit Fully-Time-Based Subranging ADC Using Highly-Linear Dynamic VTC

摘要

A novel fully-time-based subranging analog-to-digital converter (ADC) is proposed. Two time-based ADCs (TB ADCs) are used for both coarse and fine ADCs, resulting in low power operation. They were pipelined to enhance the sampling frequency. Highly-linear voltage-to-time converter (HL VTC) is also proposed to ensure a wide input range for the coarse ADC. Moreover, the interpolation time-to-digital converter (TDC) with a dynamic delayer enables low-power operation. An 8-bit test chip fabricated with 65-nm CMOS technology had power dissipation of 2.3 mW at 950 MS/s. The figure of merit was 16.0 fJ/conversion step.