Enabling technologies for 3D System on Chip (SoC) integration and examples of 3D integrated structures

摘要

3D Integration of patterned semiconductors circuits or/and integrated sensors requires some knowledge of vertical circuits stacking architecture and available technologies to realise expected by this integration performances. 3D architectures have emerged as serious contender in the challenge of functionality and potentiality increasing. Innovative circuit design, new advanced substrates, improved thin layer materials, new integration processes and technical approaches elaborated in last generation tools have grandly contributed in emerging various forms of 3D integration and packaging. In the context of More Moore and More than Moore considerations, the road maps place the vertical circuits stacking and associated post processing of stacked elements as a very serious opportunity for new generation of ICs. Furthermore, the mixing of advanced ICs with integrated passives, image sensors, mechanical and optical micro and nano-systems etc..., based on a 3D architecture have been developed during the last years. That contributes in emerging of new generation of System on Chip (SoC) with new or increased functionalities. Some of them are on the merge of commercialisation and many continued advancements and improvements are expected in the near future. In most applications cases of 3-D integration, successive staking requires the patterned wafers or dies which have already a complex integrated structures, furthermore these structures are often fragile and sensitive to the conditions of complementary processing. Therefore, before 3D integration a selection of adapted process will be done and carefully checked for its technological compatibilities.